On IDDQ Measurement Based Analysis of Bridging Faults in CMOS Circuits1

An algorithmic paradigm for I DDQ measurement based analysis that target all two node bridging faults (BFs) in CMOS circuits is presented. In contrast to the pessimistic criteria used in our prior work, here we use the criteria for identifying I DDQ tests proposed in the literature by other researchers. Algorithms for simulation, diagnosis and I DDQ subset selection of BFs in combinational circuits as well as a simulation algorithm and a subset selection algorithm for sequential circuits are presented. In addition to showing the eeciency of the proposed algorithms our preliminary experimental results suggest that: (i) for combinational circuits, our heuristic for I DDQ subset selection is considerably better than a \QUIETEST-like heuristic" for the same problem; (ii) for combinational circuits, I DDQ test sets derived from randomly generated test sets are often considerably better than I DDQ test sets derived from stuck-at test sets; and (iii) for sequential circuits, I DDQ test sets derived from randomly generated test sets are comparable to I DDQ test sets derived from stuck-at test sets.